Lead Physical Design Engineer (STA Timing)

Key Responsibilities

• Responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.
• Define and own full chip timing constraint, timing signoff criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs, and managing tape-outs day-to-day driven by development team.
• Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions.
• Deploy Timing signoff-related flows and methodologies to support production chip development. Work EDA vendors and Fabs to develop new flows and methodologies.

Key Requirements

• Bachelor Degree in Electronics or related field with minimum 10 years of relevant experiences.
• Solid hands-on experience in Static Timing Analysis, timing constraint, timing Sign-off, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, etc.
• Experience in advanced FinFET nodes (12nm & below) SoC tape out.
• Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs.
• Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).
• Good programming skills with Perl and TCL.

Key Responsibilities

• Responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.
• Define and own full chip timing constraint, timing signoff criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs, and managing tape-outs day-to-day driven by development team.
• Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions.
• Deploy Timing signoff-related flows and methodologies to support production chip development. Work EDA vendors and Fabs to develop new flows and methodologies.

Key Requirements

• Bachelor Degree in Electronics or related field with minimum 10 years of relevant experiences.
• Solid hands-on experience in Static Timing Analysis, timing constraint, timing Sign-off, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, etc.
• Experience in advanced FinFET nodes (12nm & below) SoC tape out.
• Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs.
• Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).
• Good programming skills with Perl and TCL.