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Sr Application Engineer

$ 5,800 - $ 6,300 / month

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  • Work closely with the sales team to identify and scope opportunities for the Cadence FED platform.
  • Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
  • Train, ramp-up and accompany customer project.
  • Conduct basic and advanced training, presentations and demos as necessary.
  • Ramp-up other members of the team on the advanced FED front-end technologies and tools.
  • Providing technical expertise to address clients’ queries, which need expert involvement

This position requires:

  • 5+ years’ experience in digital IC implementation including logic synthesis, physical synthesis, floorplan, placement, STA signoff.
  • Hands-on experience on running advanced process hierarchical, timing driven, SI prevention, low power place-and-route projects a big plus
  • Familiar with logic synthesis tool (DC or Genus), P&R basic knowledge of ICC or EDI, STA (Tempus), Equivalence Checking (conformal-EC or Formality), UPF/CPF concept
  • Knowledge of Linux and tcl is a must
  • Good program/engagement management skills
  • Effective team player, willing to learn
  • Work closely with the sales team to identify and scope opportunities for the Cadence FED platform.
  • Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
  • Train, ramp-up and accompany customer project.
  • Conduct basic and advanced training, presentations and demos as necessary.
  • Ramp-up other members of the team on the advanced FED front-end technologies and tools.
  • Providing technical expertise to address clients’ queries, which need expert involvement

This position requires:

  • 5+ years’ experience in digital IC implementation including logic synthesis, physical synthesis, floorplan, placement, STA signoff.
  • Hands-on experience on running advanced process hierarchical, timing driven, SI prevention, low power place-and-route projects a big plus
  • Familiar with logic synthesis tool (DC or Genus), P&R basic knowledge of ICC or EDI, STA (Tempus), Equivalence Checking (conformal-EC or Formality), UPF/CPF concept
  • Knowledge of Linux and tcl is a must
  • Good program/engagement management skills
  • Effective team player, willing to learn