Intern (ASIC Design / Design Verification)

1. Intern (Design Engineer, ASIC)

Position Overview:

Black Sesame Technologies is looking for motivated interns to join our team as Design Engineer Intern. This internship is a great opportunity for students or recent graduates to gain hands-on experience in ASIC design and contribute to the development of advanced Image Signal Processing (ISP) and Computer Vision (CV) technologies. You’ll be working closely with our experienced engineering team to support various stages of the design and verification process.

Responsibilities:

• Assist in designing micro-architecture for ISP and CV algorithms.
• Support RTL design using Verilog/SystemVerilog and HLS tools (e.g., Catapult).
• Help analyze power, performance, and area (PPA) metrics.
• Collaborate with architects and DV Engineers to support verification activities.
• Assist in FPGA-related tasks including emulation, validation, and debugging.

Qualification/ Requirements:

• Education: Pursuing or recently completed a Master’s degree in Electrical, Electronics, or Computer Engineering.
• Experience: Relevant coursework or project experience in ASIC design or image signal processing is a plus.
• Technical Skills:
• Basic knowledge of Verilog/SystemVerilog and C/C++.
• Familiarity with ASIC frontend design concepts.
• Exposure to image/vision/video data processing or algorithm acceleration is a plus.
• Experience with scripting languages (Python, Perl, Tcl) is an advantage.
• Soft Skills:
• Strong teamwork and communication skills.
• Eagerness to learn and contribute in a fast-paced, collaborative environment.
• Good analytical and problem-solving abilities.

2. Design Verification Intern

Position Overview:

We are seeking a motivated and detail-oriented Design Verification Intern to join our cutting-edge hardware engineering team. As an intern, you will work alongside senior verification engineers to support the development and execution of functional verification activities for complex ASIC designs. This is an excellent opportunity to gain hands-on experience with real-world verification methodologies, tools, and flows used in the semiconductor industry.

You’ll be exposed to a fast-paced and innovative work environment, learning from some of the best in the industry!

Responsibilities:

• Assist in the creation of testbenches using SystemVerilog and UVM under the guidance of senior engineers
• Support simulation and regression testing of RTL designs to identify and debug functional issues
• Contribute to the development of test plans based on design specifications
• Help develop or enhance scripts (e.g., Python, Perl, or TCL) to automate verification tasks and improve workflow efficiency
• Analyze simulation results, coverage reports, and help identify areas of improvement
• Attend regular team syncs and design reviews; share progress and learnings with mentors and stakeholders
• Document your work thoroughly to ensure knowledge sharing and continuity

Qualification/ Requirements:

• Education: Currently pursuing a Master’s degree or PhD in Electrical Engineering, Computer Engineering, Robotic or a related field.
• Solid Exposure to SystemVerilog or other HDLs preferred; UVM knowledge is a plus
• Familiarity with scripting languages such as Python, Perl, or TCL
• Prior coursework or experience in image processing algorithms is a plus
• Curious mindset, strong attention to detail, and eagerness to learn
• Strong communication skills and ability to work effectively in a collaborative team environment

Job Types: Full-time, Permanent

Pay: $1,000.00 - $2,000.00 per month

Schedule:

• Monday to Friday

Work Location: In person