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- Own a chip/macro layout.
- Own the overall project schedule, leveraging the design lead and layout manager as needed.
- Work effectively with various groups including layout, design, backend, frontend, ESD, packaging, CAD, etc. Represent layout within the project cross-function team with leading a team, including remote design teams
- Help implement project specific guidelines and ensure team-members follow them.
- Contribute to overall team through tool testing, script development, flow documentation, training, etc.
- Keep abreast of technology and tool developments and bring new ideas to the team.
- Bachelor’s or Master's degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience.
- Deep understanding of layout methodology from initial chip planning to tape-out.
- Deep understanding parasitic optimizing in layout
- Experiences in advanced process technology and Fin-FET is preferable.
- Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Have a high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
- Strong technical and analytical background, problem solving skills, etc.
- Fluent in English
- Team player
- Own a chip/macro layout.
- Own the overall project schedule, leveraging the design lead and layout manager as needed.
- Work effectively with various groups including layout, design, backend, frontend, ESD, packaging, CAD, etc. Represent layout within the project cross-function team with leading a team, including remote design teams
- Help implement project specific guidelines and ensure team-members follow them.
- Contribute to overall team through tool testing, script development, flow documentation, training, etc.
- Keep abreast of technology and tool developments and bring new ideas to the team.
- Bachelor’s or Master's degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience.
- Deep understanding of layout methodology from initial chip planning to tape-out.
- Deep understanding parasitic optimizing in layout
- Experiences in advanced process technology and Fin-FET is preferable.
- Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Have a high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
- Strong technical and analytical background, problem solving skills, etc.
- Fluent in English
- Team player