IC Mid-End Engineer
Salary undisclosed
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- Synthesis & Logic Optimization:
- Perform logic synthesis and design optimization for AI-focused architectures, such as tensor processing units (TPUs), NPUs, or custom accelerators.
- Work with high-speed arithmetic units (MAC arrays, systolic arrays, SIMD engines) for AI workloads.
- Static Timing Analysis (STA) & Timing Closure:
- Conduct STA, constraint tuning, and clock tree synthesis (CTS) to optimize critical paths for deep learning accelerators.
- Resolve timing issues related to multi-clock domains and high-frequency data pipelines.
- Power & Area Optimization for AI Chips:
- Implement low-power design techniques (clock gating, power gating, dynamic voltage scaling) for AI workloads.
- Work on memory hierarchy optimization (SRAM, DRAM interfaces, on-chip caches) to reduce energy consumption.
- Design-for-Test (DFT) & Debugging:
- Collaborate with DFT engineers for scan chain insertion, MBIST for large SRAMs, and JTAG integration.
- Debug synthesis, timing, and power-related design issues before physical implementation.
- Collaboration with Physical Design Team:
- Work closely with backend teams on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.
- Provide design constraints for AI-specific architectures, such as high-speed interconnects, NoCs (Network-on-Chip), and large-scale data movement.
- Formal Verification & Equivalence Checking:
- Ensure synthesized netlist correctness using formal verification tools (Conformal, FormalPro, JasperGold).
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3–7 years of experience in IC design with a focus on synthesis, timing closure, and power optimization.
- Hands-on experience with high-performance AI accelerators, NPUs, or custom compute engines.
- Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus).
- Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis.
- Familiarity with on-chip interconnect architectures (AXI, NoC, mesh, torus) for AI workloads.
- Experience in low-power design methodologies (UPF, power gating, dynamic voltage scaling).
- Proficiency in scripting (TCL, Python, Perl, Shell) for automation.
- Experience with AI compute architectures, memory optimization (HBM, SRAM, DRAM), and ASIC design for deep learning is preferred
- Familiarity with chiplet-based architectures and advanced packaging technologies like 2.5D/3D integration is preferred
- A culture that values authenticity and diversity of thoughts and backgrounds;
- An inclusive and respectable environment with open workspaces and exciting start-up spirit;
- Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
- Ability to contribute directly and make an impact on the future of the digital asset industry;
- Involvement in new projects, developing processes/systems;
- Personal accountability, autonomy, fast growth, and learning opportunities;
- Attractive welfare benefits and developmental opportunities such as training and mentoring.