Sr Design Engineer (Physical Design)
Salary undisclosed
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Job Description
• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.
Job Requirements
• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills
• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.
Job Requirements
• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills
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